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// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
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// license agreement, including, without limitation, that your use is for the 
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// agreement for further details.

module ddr5_pwrgd_logic_modular
#(
   parameter MC_SIZE = 6
)
(
// ------------------------
// Clock and Reset signals
// ------------------------
   input                    iClk,                                        //clock for sequential logic 
   input                    iRst_n,                                      //reset signal from PLL Lock, resets state machine to initial state
// ----------------------------
// inputs and outputs
// ---------------------------- 
   input                    iFM_SLPS4_N,                                 //SLP_S4 indication
	input                    iPWRGD_PS_PWROK,                             //PSU PWRGD
	
	input                    iDDRIO_PWRGD,                                //DRAMPWRGD for valid DIMM FAIL detection
	input  [MC_SIZE-1:0]     iMC_RST_N,                                   //Reset from memory controller
	input                    iDDR_GLBRST_THERMTRIP_DOWN,
	inout  [MC_SIZE-1:0]     ioPWRGD_FAIL_CH_DIMM_CPU,                    //PWRGD_FAIL bidirectional signal
	
	output [MC_SIZE-1:0]     oDIMM_MEM_FLT,                               //MEM Fault
	output [MC_SIZE-1:0]     oPWRGD_DRAMPWRGD_OK,                         //DRAM PWR OK
   output [MC_SIZE-1:0]     oFPGA_DIMM_RST_N                             //Reset to DIMMs


);

//////////////////////////////////////////////////////////////////////////////////
// Instances
//////////////////////////////////////////////////////////////////////////////////
   
	genvar                   i;
	
	generate
	   for(i=0; i<MC_SIZE; i=i+1) begin: MC
		   ddr5_pwrgd_logic ddr5_pwrgd_logic_inst(
			                                       .iClk                      (iClk),                                        //clock for sequential logic 
                                                .iRst_n                    (iRst_n),                                      //reset signal from PLL Lock, resets state machine to initial state

                                                .iFM_SLPS4_N               (iFM_SLPS4_N),                                 //SLP_S4 indication
                                                .iPWRGD_PS_PWROK           (iPWRGD_PS_PWROK),                             //PSU PWRGD
	
                                                .iDDRIO_PWRGD              (iDDRIO_PWRGD),                                //DRAMPWRGD for valid DIMM FAIL detection
                                                .iMC_RST_N                 (iMC_RST_N[i]),                                //Reset from memory controller
	                                             .iDDR_GLBRST_THERMTRIP_DOWN(iDDR_GLBRST_THERMTRIP_DOWN),
                                                .ioPWRGD_FAIL_CH_DIMM_CPU  (ioPWRGD_FAIL_CH_DIMM_CPU[i]),                 //PWRGD_FAIL bidirectional signal
	
                                                .oDIMM_MEM_FLT             (oDIMM_MEM_FLT[i]),                            //MEM Fault
                                                .oPWRGD_DRAMPWRGD_OK       (oPWRGD_DRAMPWRGD_OK[i]),                      //DRAM PWR OK
                                                .oFPGA_DIMM_RST_N          (oFPGA_DIMM_RST_N[i])                          //Reset to DIMMs
			);
		end

   endgenerate

endmodule
